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PLL

美英

n.锁相环路；多聚L-赖氨酸
网络锁相环(phase-locked loop)；锁相回路；锁相环电路

PLL

英-汉网络释义

PLL

锁相环(phase-locked loop)

锁相环（pll）：是一种实现相位自动锁定的控制系统。它一般有鉴相器、环路滤波器、压控振荡器等部件组成。

锁相回路

在锁相回路(PLL)中，相位比较器的作用类似於　(A)加法器　(B)减法器　(C)乘法器　(D)除法器。

锁相环路

先进的锁相环路(PLL)PLL (phase-locked loop)锁相环路是指这个装置中有一个由相位检测器，环路滤波器，电压控制震荡器以 …

锁相环电路

采用锁相环电路(PLL),可同时记忆18个电台. 4),视频部分(video)的特点: (1)自动识别CD和VCD碟片.(2)同时安装8枚碟片(CDC功 …

数字锁相环(Phase Lock Loop)

单数字锁相环（PLL）结构，低抖动 2千伏静电防护能力低功耗设计，应用于笔记本电脑时会尽可能的最大化电池使用时间支 …

例句：

Because of the better spur control than DDS, the Phase Locked Loop (PLL) frequency synthesis is usually used in frequency agile synthesis .

锁相频率合成（PLL ）具有比 DDS 更优秀的杂散抑制能力，常用于捷变频率合成。

Compared with the structure of the commonly used PLL circuit , that of the circuit implemented by this way is simpler and easier to be made.

用该方法实现的电路，比通常所用的锁相环电路结构简单，而且易于实现。

If the frequency offset is large enough, the traditional PLL cannot be locked . Such situation would lead to the system corruption.

当频差较大时，接收端用于载波恢复的锁相环路无法锁定，导致系统不能正常工作。

Therefore , a more thorough analysis of the output jitter , taking into account optimal loop bandwidth selection, is provided in this paper .

因此，本文在考虑最优带宽选择的情况下，对 PLL 输出时钟抖动特性进行了更深入的研究。

The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.

本文的目的是研究目前应用最广的电荷泵锁相环的噪声特性以寻找减小环路噪声的电路架构。

Application of the hardware PLL technology can achieve the synchronous sampling more effectively and help improve the sampling accuracy .

采用了硬件锁相环技术，可更加有效实现同步采样，提高了采样精度。

The second local frequency signal is provided by an integer-divider after PLL output .

二次变频的本振信号由 PLL 的输出信号经整数分频得到。

A switched varactor array is proposed to suppress tuning gain fluctuation for the performance of the phase locked loop (PLL).

该振荡器包含了一个开关可变电容阵列，用以抑制调谐增益的变化。

A fast locking phase-locked loops (PLL) with a dual-slope phase frequency detector circuit is presented .

文中提出了一种用于高速锁相环的双斜鉴频鉴相器的结构设计。

Considering the characteristics of PLL, the dual self-excited driving circuits for capacitance micro -machined gyroscope are designed .

结合锁相环的特性，设计一种电容式微机械陀螺双环路自激驱动电路。

The technology of PLL has always been the research emphasis in the field of measurement and control of power system .

锁相同步技术一直都是电力系统测控领域的研究重点。

DDS hybrid PLL can take good advantage of both their merit, have become an important area of frequency synthesis .

PLL 混合频率合成技术能综合两者的优点，已成为现今频率合成领域的重要研究方向。

The design of PLL, AGC, IQ and impedance mATched parts are analyzed . The implement of the circuit and the test result are provided .

对 PLL 、AGC 、IQ 调制以及阻抗匹配等各部分设计进行了分析，给出了具体的电路实现和测试结果。

The signal processing circuses , including the low-noise pre-amplifier, the filter and the phase lock loop(PLL) demodulation were designed.

分析并研制了系统的信号调理电路，其中包括低噪声前置放大、滤波、锁相环解调。

A detailed discussion about the hardware design including PLL, DLL of the GPS signal acquisition and tracking is focused on.

最后详细讨论了 GPS 信号接收机硬件的设计，包括捕获跟踪、PLL 、DLL 的设计。

of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks .

相位频率检测器（PFD ）和修改其他的 PLL 模块。

A novel detection method of power quality disturbance based on an improved phase-located loop (PLL) system is brought forward in this paper.

提出了一种基于改进锁相环（PLL ）系统的电能质量扰动检测方法。

The core instrument for frequency -following is the PLL. The DSP is used to realize the regulating of the dead time on-line.

用锁相环作为频率跟踪的核心器件，根据最佳死区的理论，用 DSP 实现死区的在线调节。

PLL is used for generating carry synchronization signal .

采用平方环实现载波同步信号的提取。

The PLL can provide a very wide frequency range as the input clock is fixed .

在输入时钟固定的情况下，锁相环能够输出非常宽的频率范围。

AD1896 (Analog Devices ) - selected for its low spurious tones, low distortion, and exceptionally low PLL corner frequency .

AD1896-（类比装置）为它的低点膺造的明暗，低的扭曲和例外地低的 PLL 角落频率选择。

The automatic tuning system in a PLL technique is simply introduced .

文中简单介绍了锁相环自动调谐系统。

PLL

PLL

锁相环(phase-locked loop)

锁相回路

锁相环路

锁相环电路

数字锁相环(Phase Lock Loop)

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