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时钟偏差

网络clock skew; clock skewing; clock offset

时钟偏差

时钟偏差

时钟偏差

clock skew

时钟偏差（Clock skew）和时钟树综合的概念。查看(1460) 评论(42) 2012-03-29 00:17:29 / IT/IC/电子资讯 http://www.advance…

clock skewing

程式设计语言"_馆档网 ... "时钟偏斜"," clock skew" "时钟偏差"," clock skewing" "时钟滑移"," clock slips" ...

clock offset

航海及海运专业英语词汇(C5)|无忧教育 ... clock meter 钟表式计数器 clock offset 时钟偏差 clock phase 钟脉冲 ...

Timing Distortion

Index of Electrical... ... Time Division Multiple...( 时分复用) Timing Distortion( 时钟偏差) Tin Whiskers( 锡晶须) ...

1

In multi-FPGA designs , the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance .

在多 FPGA 设计中，时钟信号的传输延时造成了 FPGA 间的大时钟偏差，进而制约系统性能。

2

Clock discrepancy information about timing discrepancies between the satellite-based clocks is also obtained (55 ).

还得到关于 *基于 *时钟间的定时偏差的时钟偏差信息（55 ）。

4

Clock drift can also be (deliberately ) caused by the activity of the DTSS or NTP packages .

时钟偏差也可能是（故意）执行 DTSS 或 NTP 包所造成。

5

Based on the layout static timing analysis , the clock period was optimized by the clock skew scheduling utilizing the DCCB.

利用此特性，基于电路版图时序分析，通过重构 DCCB 单元进行时钟偏差调整，优化时钟周期。

6

In clock routing , clock signal and clock skew become more and more important for impact of the circuit performance .

在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。

7

Clock Skew Scheduling with Tolerance of Process Variations

抗工艺变化的时钟偏差规划

8

Effect of Sampling Clock Offsets on the Performance of OFDM System

采样时钟偏差对 OFDM 系统性能的影响

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